View M93S56_299220.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M93S66, M93S56, M93S46
4K/2K/1K (x16) Serial Microwire Bus EEPROM with Block Protection
INDUSTRY STANDARD MICROWIRE BUS 1 MILLION ERASE/WRITE CYCLES, with 40 YEARS DATA RETENTION SINGLE ORGANIZATION by WORD (x16) WORD and ENTIRE MEMORY PROGRAMMING INSTRUCTIONS SELF-TIMED PROGRAMMING CYCLE with AUTO-ERASE READY/BUSY SIGNAL DURING PROGRAMMING SINGLE SUPPLY VOLTAGE: - 4.5V to 5.5V for M93Sx6 version - 2.5V to 5.5V for M93Sx6-W version - 1.8V to 3.6V for M93Sx6-R version USER DEFINED WRITE PROTECTED AREA PAGE WRITE MODE (4 words) SEQUENTIAL READ OPERATION 5ms TYPICAL PROGRAMMING TIME ENHANCED ESD and LATCH-UP PERFORMANCES DESCRIPTION This M93S46/S56/S66 specification covers a range of 4K/2K/1K bit serial EEPROM products respectively. In this text, products are referred to as M93Sx6. The M93Sx6 is an Electrically Erasable Programmable Memory (EEPROM) fabricated with STMicroelectronics's High Endurance Single Polysilicon CMOS technology. Table 1. Signal Names
S D Q C PRE W VCC VSS Chip Select Input Serial Data Input Serial Data Output Serial Clock Protect Enable Write Enable Supply Voltage Ground
8 1
PSDIP8 (BN) 0.25mm Frame
8 1
SO8 (MN) 150mil Width
8 1
TSSOP8 (DW) 169mil Width
Figure 1. Logic Diagram
VCC
D C S PRE W M93Sx6 Q
VSS
AI02020
February 1999
1/23
M93S66, M93S56, M93S46
Figure 2A. DIP Pin Connections Figure 2B. SO and TSSOP Pin Connections
M93Sx6 S C D Q 1 2 3 4 8 7 6 5
AI02021
M93Sx6
VCC PRE W VSS
S C D Q
1 2 3 4
8 7 6 5
AI02022
VCC PRE W VSS
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering (SO8 package) (PSDIP8 package) 40 sec 10 sec Value -40 to 125 -65 to 150 215 260 -0.3 to VCC +0.5 -0.3 to 6.5 4000 500 Unit C C C V V V V
Input or Output Voltages (Q = VOH or Hi-Z) Supply Voltage Electrostatic Discharge Voltage (Human Body model) (2) Electrostatic Discharge Voltage (Machine model)
(3)
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500 ). 3. EIAJ IC-121 (Condition C) (200pF, 0 ).
DESCRIPTION (cont'd) The M93Sx6 memory is accessed through a serial input (D) and output (Q) using the MICROWIRE bus protocol. The M93Sx6 is specified at 5V 10%, the M93Sx6-W specified at 2.5V to 5.5V and the M93Sx6-R specified at 1.8V to 3.6V. The M93S66/S56/S46 memory is divided into 256/128/64 x16 bit words respectively. These memory devices are available in both PSDIP8, SO8 and TSSOP8 packages. The M93Sx6 memory is accessed by a set of instructions which includes Read, Write, Page
Write, Write All and instructions used to set the memory protection. A Read instruction loads the address of the first word to be read into an internal address pointer. The data contained at this address is then clocked out serially. The address pointer is automatically incremented after the data is output and, if the Chip Select input (S) is held High, the M93Sx6 can output a sequential stream of data words. In this way, the memory can be read as a data stream from 16 to 4096 bits (for the M93S66), or continuously as the address counter automatically rolls over to '00' when the highest address is reached.
2/23
M93S66, M93S56, M93S46
Table 3. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages (M93Sxx) Input Pulse Voltages (M93Sxx-W, M93Sxx-R) Input Timing Reference Voltages (M93Sxx) Output Timing Reference Voltages (M93Sxx) Input and Output Timing Reference Voltages (M93Sxx-W, M93Sxx-R) Output Load
Note that Output Hi-Z is defined as the point where data is no longer driven.
50ns 0.4V to 2.4V 0.2VCC to 0.8VCC 1.0V to 2.0V 0.8V to 2.0V 0.3VCC to 0.7VCC C L = 100pF
Table 4. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 5 5 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Within the time required by a programming cycle (tW), up to 4 words may be written with help of the Page Write instruction. the whole memory may also be erased, or set to a predetermined pattern, by using the Write All instruction. Within the memory, an user defined area may be protected against further Write instructions. The size of this area is defined by the content of a Protect Register, located outside of the memory array. As a final protection step, data may be permanently protected by programming a One Time Programming bit (OTP bit) which locks the Protect Register content. Programming is internally self-timed (the external clock signal on C input may be disconnected or left running after the start of a Write cycle) and does not require an erase cycle prior to the Write instruction. The Write instruction writes 16 bits at one time int o one of the 256/128/64 words of the M93S46/S56/S66 respectively, the Page Write instruction writes up to 4 words of 16 bits to sequential locations, assuming in both cases that all addresses are outside the Write Protected area. After the start of the programming cycle, a Ready/Busy signal is available on the Data output (Q) when Chip Select (S) is driven High. An internal feature of the M93Sx6 provides Poweron Data Protection by inhibiting any operation
Figure 3. AC Testing Input Output Waveforms
M93SXX 2.4V 2V 1V 0.4V INPUT OUTPUT 2.0V 0.8V
M93SXX-W & M93SXX-R 0.8VCC 0.7VCC 0.3VCC
AI02791
0.2VCC
when the Supply is too low. The design of the M93Sx6 and the High Endurance CMOS technology used for its fabrication give an Erase/Write cycle Endurance of 1,000,000 cycles and a data retention of 40 years.
3/23
M93S66, M93S56, M93S46
Table 5A. DC Characteristics for M93Sx6 (TA = 0 to 70C or -40 to 85C; VCC = 4.5V to 5.5V)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) Input Low Voltage (D, C, S, W, PRE) Input High Voltage (D, C, S, W, PRE) Output Low Voltage (Q) Output High Voltage (Q) VCC = 5V, IOL = 2.1mA VCC = 5V, IOH = -400A 2.4 Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz VCC = 5V, S = VSS, C = VSS, W = VSS or VCC, PRE = VSS or VCC -0.3 2 Min Max 2.5 2.5 1.5 50 0.8 VCC + 1 0.4 Unit A A mA A V V V V
Table 5B. DC Characteristics for M93Sx6 (TA = -40 to 125C; VCC = 4.5V to 5.5V)
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) Input Low Voltage (D, C, S, W, PRE) Input High Voltage (D, C, S, W, PRE) Output Low Voltage (Q) Output High Voltage (Q) VCC = 5V, IOL = 2.1mA VCC = 5V, IOH = -400A 2.4 Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz VCC = 5V, S = VSS, C = VSS, W = VSS or VCC, PRE = VSS or VCC -0.3 2 Min Max 2.5 2.5 1.5 50 0.8 VCC + 1 0.4 Unit A A mA A V V V V
4/23
M93S66, M93S56, M93S46
Table 5C. DC Characteristics for M93Sx6-W (TA = 0 to 70C or -40 to 85C; VCC = 2.5V to 5.5V)
Symbol ILI ILO ICC Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 5V, S = VIH, f = 1 MHz VCC = 2.5V, S = VIH, f = 1 MHz ICC1 VIL VIH VOL Supply Current (Standby) Input Low Voltage (D, C, S, W, PRE) Input High Voltage (D, C, S, W, PRE) Output Low Voltage (Q) VCC = 5V, IOL = 2.1mA VCC = 2.5V, IOL = 100A VOH Output High Voltage (Q) VCC = 5V, IOH = -400A VCC = 2.5V, IOH = -100A 2.4 VCC - 0.2 VCC = 2.5V, S = VSS, C = VSS, W = VSS or VCC, PRE = VSS or VCC -0.3 0.7 VCC Min Max 2.5 2.5 1.5 1 10 0.2 VCC VCC + 1 0.4 0.2 Unit A A mA mA A V V V V V V
Table 5D. DC Characteristics for M93Sx6-R (1) (TA = 0 to 70C or -20 to 85C; VCC = 1.8V to3.6V)
Symbol ILI ILO ICC Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS Inputs) Test Condition 0V VIN VCC 0V VOUT VCC, Q in Hi-Z VCC = 3.6V, S = VIH, f = 1 MHz VCC = 1.8V, S = VIH, f = 1 MHz ICC1 VIL VIH VOL VOH Supply Current (Standby) Input Low Voltage (D, C, S, W, PRE) Input High Voltage (D, C, S, W, PRE) Output Low Voltage (Q) Output High Voltage (Q) VCC = 1.8V, IOL = 100A VCC = 1.8V, IOH = -100A VCC - 0.2 VCC = 1.8V, S = VSS, C = VSS, W = VSS or VCC, PRE = VSS or VCC -0.3 0.8 VCC Min Max 2.5 2.5 1.5 1 5 0.2 VCC VCC + 1 0.2 Unit A A mA mA A V V V V
Note: 1. This is preliminary data.
5/23
M93S66, M93S56, M93S46
Table 6A. AC Characteristics
M93S66/56/46 Symbol Alt Parameter VCC = 4.5V to 5.5V, TA = 0 to 70C, TA = -40 to 85C Min tPRVCH tWVCH tSHCH tCLSH tDVCH tCHDX tCHQL tCHQV tCLPRX tSLWX tCLSL tSLCH tSLSH
(1)
VCC = 4.5V to 5.5V, TA = -40 to 125C Min 50 50 50 100 100 100 Max
Unit
Max
tPRES tPES tCSS tSKS tDIS tDIH tPD0 tPD1 tPREH tPEH tCSH
Protect Enable Valid to Clock High Write Enable Valid to Clock High Chip Select Set-up Time Clock Set-up Time (relative to S) Data In Set-up Time Data In Hold Time Delay to Output Low Delay to Output Valid Clock Low to Protect Enable Transition Chip Select Low to Write Enable Transition Chip Select Hold Time Chip Select Low to Clock High
50 50 50 100 100 100 400 400 0 250 0 250 250 400 200 250 250 10 0 1
ns ns ns ns ns ns 400 400 ns ns ns ns ns ns ns 400 200 ns ns ns ns 10 ms MHz
0 250 0 250 250
tCS tSV tDF tSKH tSKL tWP fSK
Chip Select Low to Chip Select High Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Clock High Time Clock Low Time Erase/Write Cycle time Clock Frequency
tSHQV tSLQZ tCHCL tCLCH tW fC
(2) (2)
250 250
0
1
Notes: 1. Chip Select must be brought low for a minimum of tSLSH between consecutive instructions cycles. 2. The Clock frequency specification calls for a minimum clock period of 1/fC, therefore the sum of the timings tCHCL+tCLCH must be greater or equal to 1/fC.
6/23
M93S66, M93S56, M93S46
Table 6B. AC Characteristics
M93S66/56/46 Symbol Alt Parameter VCC = 2.5V to 5.5V, TA = 0 to 70C, TA = -40 to 85C Min tPRVCH tWVCH tSHCH tCLSH tDVCH tCHDX tCHQL tCHQV tCLPRX tSLWX tCLSL tSLCH tSLSH
(1)
VCC = 1.8V to 3.6V, (3) TA = 0 to 70C TA = -20 to 85C Min 50 50 200 100 100 200 Max
Unit
Max
tPRES tPES tCSS tSKS tDIS tDIH tPD0 tPD1 tPREH tPEH tCSH
Protect Enable Valid to Clock High Write Enable Valid to Clock High Chip Select Set-up Time Clock Set-up Time (relative to S) Data In Set-up Time Data In Hold Time Delay to Output Low Delay to Output Valid Clock Low to Protect Enable Transition Chip Select Low to Write Enable Transition Chip Select Hold Time Chip Select Low to Clock High
50 50 100 100 100 100 400 400 0 250 0 250 250 400 200 350 250 10 0 1
ns ns ns ns ns ns 700 700 ns ns ns ns ns ns ns 700 200 ns ns ns ns 10 ms MHz
0 250 0 250 1000
tCS tSV tDF tSKH tSKL tWP fSK
Chip Select Low to Chip Select High Chip Select to Ready/Busy Status Chip Select Low to Output Hi-Z Clock High Time Clock Low Time Erase/Write Cycle time Clock Frequency
tSHQV tSLQZ tCHCL tCLCH tW fC
(2) (2)
800 800
0
0.5
Notes: 1. Chip Select must be brought low for a minimum of tSLSH between consecutive instructions cycles. 2. The Clock frequency specification calls for a minimum clock period of 1/fC, therefore the sum of the timings tCHCL+tCLCH must be greater or equal to 1/fC. 3. This is preliminary data.
7/23
M93S66, M93S56, M93S46
Figure 4. Synchronous Timing, Start and Op-Code Input
PRE tPRVCH W tWVCH C tCLSH S tDVCH D START OP CODE tCHDX OP CODE tSHCH tCLCH tCHCL
OP CODE INPUT START
AI02025
POWER-ON DATA PROTECTION In order to prevent data corruption and inadvertent write operations during power-up and power-down, a Power On Reset (POR) circuit resets all internal programming circuitry and sets the device in the Write Disable mode. - At Power-up and Power-down, the device must NOT be selected (that is, the S input must be driven low) until the supply voltage reaches the operating value Vcc specified in the AC and DC tables.
- When VCC reaches its functional value, the device is properly reset (in the Write Disable mode) and is ready to decode and execute an incoming instruction. For the M93Sx6 specified at 5V, the POR threshold voltage is around 3V. For all the other M93Sx6 specified at low VCC (with -W and -R VCC range options), the POR threshold voltage is around 1.5V.
8/23
M93S66, M93S56, M93S46
Figure 5. Synchronous Timing, Read or Write
C tCLSL S tDVCH D An tCHQL Q15 tCHDX A0 tSLQZ Q0 tCHQV tSLSH
Hi-Z Q
ADDRESS INPUT
DATA OUTPUT
AI002026
PRE tCLPRX W tSLWX C tSLCH tCLSL S tSLSH tDVCH D An tCHDX A0/D0 tSHQV Hi-Z Q BUSY tW ADDRESS/DATA INPUT WRITE CYCLE
AI02027
tSLQZ READY
9/23
M93S66, M93S56, M93S46
INSTRUCTIONS The M93S66/S56/S46 have eleven instructions, as shown in Table 7. Each instruction is preceded by the rising edge of the signal applied on the Chip Select (S) input (assuming that the clock C is low). After the device is selected, the internal logic waits for the start bit, which define the begining of the instruction bit stream. The start bit is the first '1' read on D input during the rising edge of the clock C. Following the start bit, the op-codes of the instructions are made up of the 2 following bits. Notice that some instructions use only these first two bits, others use also the first two bits of the address to define the op-code. The op-code is then followed by the address of the word to be accessed. For the M93S46, the address is made up of 6 bits (See Table 7a). For the M93S56 and M93S66, the address is made up of 8 bits (See Table 7b). The M93Sx6 is fabricated in CMOS technology and is therefore able to run from zero Hz (static input signals) up to the maximum ratings (specified in Table 6).
Table 7A. Instruction Set for the M93S46
Instr. Description Read Data from Memory Write Data to Memory W PRE Start Bit '1' OpCode 10 Address (1) Data Req. Clock Cycles Additional Information
READ
X
'0'
A5-A0
Q15-Q0 Write is executed if the address is not inside the Protected area Write is executed if all the N addresses are not inside the Protected area Write all data if the Protect Register is cleared
WRITE
'1'
'0'
'1'
01
A5-A0
D15-D0
25
PAWRITE
Page Write to Memory
'1'
'0'
'1'
11
A5-A0
Nx D15-D0
9+N x 16
WRALL WEN WDS
Write All Memory Write Enable Write Disable
'1' '1' X
'0' '0' '0'
'1' '1' '1'
00 00 00
01XXXX 11XXXX 00XXXX
D15-D0
25 9 9
Protect PRREAD Register Read
X
'1'
'1'
10
XXXXXX
Q5-Q0 + Flag
Data Output = Protect Register content + Protect Flag bit Data above specified address A5-A0 are protected Protect Flag is also cleared (cleared Flag = 1)
PRWRITE
Protect Register Write
'1'
'1'
'1'
01
A5-A0
9
PRCLEAR
Protect Register Clear Protect Register Enable Protect Register Disable
'1'
'1'
'1'
11
111111
9
PREN
'1'
'1'
'1'
00
11XXXX
9 OTP bit is set permanently
PRDS
'1'
'1'
'1'
00
000000
9
Note: 1. X = don't care bit.
10/23
M93S66, M93S56, M93S46
Table 7B. Instruction Set for the M93S56 and M93S66
Instr. Description Read Data from Memory Write Data to Memory W PRE Start Bit '1' OpAddress (1,2) Code 10 A7-A0 Data Req. Clock Cycles Additional Information
READ
X
'0'
Q15-Q0 Write is executed if the address is not inside the Protected area Write is executed if all the N addresses are not inside the Protected area Write all data if the Protect Register is cleared
WRITE
'1'
'0'
'1'
01
A7-A0
D15-D0
27
Page Write to PAWRITE Memory
'1'
'0'
'1'
11
A7-A0
Nx D15-D0
11 + N x 16
WRALL WEN WDS
Write All Memory Write Enable Write Disable Protect Register Read
'1' '1' X
'0' '0' '0'
'1' '1' '1'
00 00 00
01XXXXXX 11XXXXXX 00XXXXXX
D15-D0
27 11 11
PRREAD
X
'1'
'1'
10
XXXXXXXX
Q7-Q0 + Flag
Data Output = Protect Register content + Protect Flag bit Data above specified address A7-A0 are protected Protect Flag is also cleared (cleared Flag = 1)
PRWRITE
Protect Register Write
'1'
'1'
'1'
01
A7-A0
11
PRCLEAR
Protect Register Clear Protect Register Enable Protect Register Disable
'1'
'1'
'1'
11
11111111
11
PREN
'1'
'1'
'1'
00
11XXXXXX
11 OTP bit is set permanently
PRDS
'1'
'1'
'1'
00
00000000
11
Notes: 1. X = don't care bit. 2. Address bit A7 is not decoded by the M93S56.
11/23
M93S66, M93S56, M93S46
Read The Read instruction (READ) outputs serial data on the Data Output (Q). When a READ instruction is received, the instruction and address are decoded and the data from the memory is transferred into an output shift register. A dummy '0' bit is output first followed by the 16 bit word with the MSB first. Output data changes are triggered by the Low to High transition of the Clock (C). The M93Sx6 will automatically increment the address and will clock out the next word as long as the Chip Select input (S) is held High. In this case the dummy '0' bit is NOT output between words and a continuous stream of data can be read. Write Enable and Write Disable The Write Enable instruction (WEN) authorizes the following Write instructions to be executed. The Write Disable instruction (WDS) disables the execution of the following Write instructions and the internal programming cycle cannot run. When power is first applied, the M93Sx6 is in Write Disable mode and all Write instructions are inhibited. When the WEN instruction is executed, Write instructions remain enabled until a Write Disable instruction (WDS) is executed or VCC falls below the Power-On Reset threshold Voltage. To protect the memory contents from accidental corruption, it is advisable to issue the WDS instruction after every write cycle. The READ instruction is not affected by the WEN or WDS instructions. Write The Write instruction (WRITE) is composed of the Start bit plus the Op-Code followed by the address and the 16 data bits to be written. The Write Enable signal (W) must be held high during the Write instruction. Data input (D) is sampled on the Low to High transition of the clock. After the last data bit has been sampled, Chip Select (S) must be brought Low before the next rising edge of the clock (C) in order to start the self-timed programming cycle. This is really important as, if S is brought low before or after this specific frame window, the addressed location will not be programmed, providing that the address in NOT in the protected area. If the M93Sx6 is still performing the write cycle, the Busy signal (Q = 0) will be returned if the Chip Select input (S) is driven high after the tSLSH delay, and the M93Sx6 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the M93Sx6 is ready to receive a new instruction. Programming is internally self-timed (the external clock signal on C input may be disconnected or left running after the start of a Write cycle). Page Write A Page Write instruction (PAWRITE) contains the first address to be written followed by up to 4 data words. The Write Enable signal (W) must be held High during the PAWRITE instruction. Input address and data are sampled on the Low to High transition of the clock. After the receipt of each data word, bits A1-A0 of the internal address register are incremented, the high order bits (Ax-A2) remaining unchanged. Users must take care by software to ensure that the last word address has the same upper order address bits as the initial address transmitted to avoid address roll-over. After the LSB of the last data word, Chip Select (S) must be brought Low before the next rising edge of the Clock (C) in order to start the self-timed programming cycle. This is really important as, if S is brought low before or after this specific frame window, the addressed locations will not be programmed. The Page Write operation will not be performed if any of the 4 words is addressing the protected area. If the M93Sx6 is still performing the programming cycle, the Busy signal (Q = 0) will be returned if the Chip Select input (S) is driven high, and the M93Sx6 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the M93Sx6 is ready to receive a new instruction. Write All The Write All instruction (WRALL) is valid only after the Protect Register has been cleared by executing a PRCLEAR (Protect Register Clear) instruction. The Write All instruction simultaneously writes the whole memory with the same data word included in the instruction. The Write Enable signal (W) must be held High before and during the Write All instruction. Input address and data are sampled on the Low to High transition of the clock. If the M93Sx6 is still performing the write cycle, the Busy signal (Q = 0) will be returned if the Chip Select input (S) is driven high after the tSLSH delay, and the M93Sx6 will ignore any data on the bus. When the write cycle is completed, the Ready signal (Q = 1) will indicate (if S is driven high) that the M93Sx6 is ready to receive a new instruction. READY/BUSY Status During every programming cycle (after a WRITE, WRALL or PAWRITE instruction) the Data Output (Q) indicates the Ready/Busy status of the memory when the Chip Select is driven High. Once the M93Sx6 is Ready, the Data Output is set to '1' until a new start bit is decoded or the Chip Select is brought Low.
12/23
M93S66, M93S56, M93S46
MEMORY WRITE PROTECTION AND PROTECT REGISTER The M93Sx6 offers a Protect Register containing the bottom address of the memory area which has to be protected against write instructions. In addition to this Protect Register, two flag bits are used to indicate the Protect Register status: the Protect Flag enabling/disabling the memory protection throught the Protect Register and the OTP bit which, when set, disables access to the Protect Register and thus prevents any further modifications of this Protect Register value. The content of the Protect Register is defined when using the PRWRITE instruction, it may be read when using the PRREAD instruction. A specific instruction PREN (Protect Register Enable) allows the user to execute the protect instructions PRCLEAR, PRWRITE and PRDS. this PREN instruction being used together with the signals applied on the input pins PRE (Protect Register Enable) and W (Write Enable). Accessing the Protect Register is done by executing the following sequence: - WEN: execute the Write Enable instruction, - PREN: execute the PREN instruction, - PRWRITE, PRCLEAR or PRDS: the protection then may be defined, in terms of size of the protected area (PRWRITE, PRCLEAR) and may be set permanently (PRDS instruction). Protect Register Read The Protect Register Read instruction (PRREAD) outputs on the Data Output Q the content of the Protect Register, followed by the Protect Flag bit. The Protect Register Enable pin (PRE) must be driven High before and during the instruction. As in the Read instruction a dummy '0' bit is output first. Since it is not possible to distinguish if the Protect Register is cleared (all 1's) or if it is written with all 1's, user must check the Protect Flag status (and not the Protect Register content) to ascertain the setting of the memory protection. Protect Register Enable The Protect Register Enable instruction (PREN) is used to authorize the use of further PRCLEAR, PRWRITE and PRDS instructions. The PREN insruction does not modify the Protect Flag bit value. Note: A Write Enable (WEN) instruction must be executed before the Protect Enable instruction. Both the Protect Enable (PRE) and Write Enable (W) input pins must be held High during the instruction execution. Protect Register Clear The Protect Register Clear instruction (PRCLEAR) clears the address stored in the Protect Register to all 1's, and thus enables the execution of WRITE and WRALL instructions. The Protect Register Clear execution clears the Protect Flag to '1'. Both the Protect Enable (PRE) and Write Enable (W) input pins must be driven High during the instruction execution. Note: A PREN instruction must immediately precede the PRCLEAR instruction. Protect Register Write The Protect Register Write instruction (PRWRITE) is used to write into the Protect Register the address of the first word to be protected. After the PRWRITE instruction execution, all memory locations equal to and above the specified address, are protected from writing. The Protect Flag bit is set to '0', it can be read with Protect Register Read instruction. Both the Protect Enable (PRE) and Write Enable (W) input pins must be driven High during the instruction execution. Note: A PREN instruction must immediately precede the PRWRITE instruction, but it is not necessary to execute first a PRCLEAR. Protect Register Disable The Protect Register Disable instruction sets the One Time Programmable bit (OTP bit). The Protect Register Disable instruction (PRDS) is a ONE TIME ONLY instruction which latches the Protect Register content, this content is therefore unalterable in the future. Both the Protect Enable (PRE) and Write Enable (W) input pins must be driven High during the instruction execution. The OTP bit cannot be directly read, it can be checked by reading the content of the Protect Register (PRREAD instruction), then by writing this same value into the Protect Register (PRWRITE instruction): when the OTP bit is set, the Ready/Busy status cannot appear on the Data output (Q). When the OTP bit is not set, the Busy status appear on the Data output (Q). Note: A PREN instruction must immediately precede the PRDS instruction.
13/23
M93S66, M93S56, M93S46
Figure 6. READ, WRITE, WEN, WDS Sequences
READ
PRE
S
D
1 1 0 An
A0
Q ADDR OP CODE
Qn DATA OUT
Q0
WRITE
PRE
W
S CHECK STATUS D 1 0 1 An A0 Dn D0
Q ADDR OP CODE DATA IN BUSY READY
WRITE ENABLE
PRE
WRITE DISABLE
PRE
W
S
S
D
1 0 0 0 0 Xn X0
D
1 0 0 1 1 Xn X0
OP CODE
OP CODE
AI00889D
Notes: 1. An - Xn - Qn - Dn: Refer to Table 7a for the M93S46. 2. An - Xn - Qn - Dn: Refer to Table 7b for the M93S56 and M93S66.
14/23
M93S66, M93S56, M93S46
Figure 7. PAWRITE, WRALL Sequences
PAGE WRITE
PRE
W
S CHECK STATUS D 1 1 1 An A0 Dn D0
Q ADDR OP CODE DATA IN BUSY READY
WRITE ALL
PRE
W
S CHECK STATUS D 1 0 0 0 1 Xn X0 Dn D0
Q ADDR OP CODE
AI00890C
DATA IN
BUSY
READY
Notes: 1. An - Xn - Dn: Refer to Table 7a for the M93S46. 2. An - Xn - Dn: Refer to Table 7b for the M93S56 and M93S66.
15/23
M93S66, M93S56, M93S46
Figure 8. PRREAD, PRWRITE, PREN Sequences
Protect Register READ
PRE
S
D
1 1 0 Xn
X0
Q ADDR OP CODE
An
A0 F DATA OUT F = Protect Flag
Protect Register WRITE
PRE
W
S CHECK STATUS D 1 0 1 An A0
Q ADDR OP CODE BUSY READY
Protect Register ENABLE
PRE
W
S
D
1 0 0 1 1 Xn X0
OP CODE
AI00891D
Notes: 1. An - Xn - Dn: Refer to Table 7a for the M93S46. 2. An - Xn - Dn: Refer to Table 7b for the M93S56 and M93S66.
16/23
M93S66, M93S56, M93S46
Figure 9. PRCLEAR, PRDS Sequences
Protect Register CLEAR
PRE
W
S CHECK STATUS D 111 111
Q ADDR OP CODE BUSY READY
Protect Register DISABLE
PRE
W
S CHECK STATUS D 100 000
Q ADDR OP CODE
AI00892C
BUSY
READY
Notes: 1. An - Xn - Dn: Refer to Table 7a for the M93S46. 2. An - Xn - Dn: Refer to Table 7b for the M93S56 and M93S66.
17/23
M93S66, M93S56, M93S46
COMMON I/O OPERATION The Data Output (Q) and Data Input (D) signals can be connected together, through a current limiting resistor, to form a common, one wire data bus. Some precautions must be taken when operating the memory with this connection, mostly to prevent a short circuit between the last entered address bit (A0) and the first data bit output by Q. The reader should refer to the STMicroelectronics application note AN394 "MICROWIRE EEPROM Common I/O Operation". CLOCK PULSE COUNTER The M93Sx6 offers a functional security filtering glitches on the clock input (C), the clock pulse counter. In a normal environment, the M93Sx6 expectes to receive the exact amount of data on the D input (start bit, Op-Code, Address, Data), that is the exact amount of clock pulses on the C input. In a noisy environment, the number of pulses received (on the clock input C) may be greater than the clock pulses delivered by the Master (Microcontroller) driving the M93Sx6. In such a case, a part of the instruction is delayed by one bit (see Figure 10), and it may induce an erroneous write of data at a wrong address. The M93Sx6 has an on-chip counter which counts the clock pulses from the Start bit until the falling edge of the Chip Select signal. For the WRITE instructions with a M93S56 (or M93S66), the number of clock pulses incoming to the counter must be exactly 27 from the Start bit to the falling edge of Chip Select signal (1 Start bit + 2 Op-code bit + 8 Address bit + 16 Data bit = 27): if so, the M93S56 (or M93S66) executes the WRITE instruction. If the number of clock pulses is not equal to 27, the instruction will not be executed (and data will not be corrupted). The clock pulse counter is active on WRITE, PAWRITE, WRALL, PRWRITE and PRCLEAR instructions. In order to determine the exact number of clock pulses needed for all the M93Sx6 on WRITE instructions, refer to Tables 7a and 7b, in the column: Requested Clock Cycles.
Figure 10. Write Sequence with One Clock Glitch
S
C
D
An START "0" WRITE "1"
An-1 Glitch
An-2 D0
ADDRESS AND DATA ARE SHIFTED BY ONE BIT
AI01395
18/23
M93S66, M93S56, M93S46
ORDERING INFORMATION SCHEME Example: M93S56 - W MN 6 T
Memory Density 66 4 Kbit 56 2 Kbit 46 1 Kbit
Operating Voltage blank 4.5V to 5.5V W 2.5V to 5.5V R (3) 1.8V to 3.6V
Package BN PSDIP8 0.25mm Frame MN SO8 150mil Width DW TSSOP8 169mil Width
Temperature Range 1
(1)
Option T Tape & Reel Packing
0 to 70 C -20 to 85 C -40 to 85 C -40 to 125 C
5 6 3
(2)
Notes: 1. Temperature range on request only. 2. Produced with High Reliability Certified Flow (HRCF), in VCC range 4.5V to 5.5V at 1MHz only. 3. -R version (1.8V to 3.6V) are only available in temperature ranges 5 or 1.
Devices are shipped from the factory with the memory content set at all "1's" (FFFFh). For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
19/23
M93S66, M93S56, M93S46
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm Typ A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 Min 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ inches Min 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150
Symb
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Drawing is not to scale
20/23
M93S66, M93S56, M93S46
SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Typ A A1 B C D E e H h L N CP 1.27 Min 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ inches Min 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8
Symb
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Drawing is not to scale
21/23
M93S66, M93S56, M93S46
TSSOP8 - 8 lead Plastic Shrink Small Outline, 169 mils body width
mm Typ A A1 A2 B C D E E1 e L N CP 0.65 0.05 0.85 0.19 0.09 2.90 6.25 4.30 - 0.50 0 8 0.08 Min Max 1.10 0.15 0.95 0.30 0.20 3.10 6.50 4.50 - 0.70 8 0.026 0.002 0.033 0.007 0.004 0.114 0.246 0.169 - 0.020 0 8 0.003 Typ inches Min Max 0.043 0.006 0.037 0.012 0.008 0.122 0.256 0.177 - 0.028 8
Symb
D
N
DIE
C
E1 E
1
N/2
A1
A A2
L
CP
Drawing is not to scale
B
e TSSOP
22/23
M93S66, M93S56, M93S46
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
23/23

▲Up To Search▲

Price & Availability of M93S56

	To Download M93S56 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .